Defective memory block identification in a memory device

ABSTRACT

During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location.

RELATED APPLICATION

This a Continuation of U.S. application Ser. No. 12/568,912 titled“DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE,” filed Sep.29, 2009 (allowed), which is a Continuation of U.S. application Ser. No.11/454,464, filed Jun. 16, 2006, U.S. Pat. No. 7,610,525 issued on Oct.27, 2009, which is a Continuation of U.S. application Ser. No.10/930,087, filed Aug. 31, 2004, U.S. Pat. No. 7,272,458 issued on Sep.18, 2007 which are commonly assigned and incorporated herein byreference.

TECHNICAL FIELD

The present invention relates generally to memory devices and inparticular the present invention relates to a flash memory devices.

BACKGROUND

Memory devices are typically internal, semiconductor, integratedcircuits in computers or other electronic devices. There are manydifferent types of memory including random-access memory (RAM), readonly memory (ROM), dynamic random access memory (DRAM), synchronousdynamic random access memory (SDRAM), and flash memory.

Flash memory devices have developed into a popular source ofnon-volatile memory for a wide range of electronic applications. Flashmemory devices typically use a one-transistor memory cell that allowsfor high memory densities, high reliability, and low power consumption.Common uses for flash memory include personal computers, personaldigital assistants (PDAs), digital cameras, and cellular telephones.Program code and system data such as a basic input/output system (BIOS)are typically stored in flash memory devices for use in personalcomputer systems.

Unlike most semiconductor memory, flash memory devices can be sold witha limited quantity of defective memory blocks. Flash memory devicestypically have a scheme to communicate the locations of the defectiveblocks to a controller or processor.

One such scheme employs markers at specific locations in the defectivememory block. The markers are generated during the manufacturing andtesting process before being sold to the user. When the user powers-upthe memory device, the memory controller would go through these specificlocations in memory and track the defective blocks. Since there can beover 2000 memory blocks in a typical memory device, this is considerableoverhead for the controller to handle.

In another error detection scheme, the memory controller reads thememory cells in a memory block and if the data is anything but FFH itwould consider that block as a bad block. The controller then moves onto the next block. When all of the block's memory locations are read asFFH, the controller considers that block as good and starts to extractthe information that it expected to see in block 0.

However, if the memory defect is such that the controller is incapableof writing to any location in that block, the FFH data could not bealtered from the initial erased condition. In this case, the controllerwould assume that the block is good since it read an FFH. Upon trying towrite desired data into this block, the system would not allow it due tothe write defect.

For the reasons stated above, and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foran improved method for handling defective memory locations with minimalcontroller overhead.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a flowchart of one embodiment of a method for indicatingdefective memory blocks in a flash memory device.

FIG. 2 shows a schematic diagram of one embodiment of a NAND flashmemory array of the present invention.

FIG. 3 shows a block diagram of one embodiment of an electronic systemof the present invention.

DETAILED DESCRIPTION

In the following detailed description of the invention, reference ismade to the accompanying drawings that form a part hereof and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The followingdetailed description is, therefore, not to be taken in a limiting sense,and the scope of the present invention is defined only by the appendedclaims and equivalents thereof.

FIG. 1 illustrates a flowchart of one embodiment of a method foridentifying defective memory blocks in a flash memory device. In oneembodiment, this method would be performed during the manufacturing andtesting processes at the memory device manufacturer. This reduces theoverhead operations required of the memory controller once the userbegins operating the device.

The method performs a memory check 101 to determine if any defectiveblocks are present in the memory array. This memory check is well knownin the art and can comprise writing a predetermined pattern to thememory cells then reading the data out. If the pattern that was read outdoes not match what was written, the location is considered defectiveand the block should be marked as defective. The error detection mayalso check for bitlines that are shorted together, multilevel cells thathave one or more defective bits, or other types of errors. The presentinvention is not limited to any one error checking routine.

If a defective memory cell or cells were discovered 103, the memory iserased 105 and the block number or numbers containing the defectivelocations are stored 107. The memory needs to be erased due to thepatterns left in the memory from the memory check process. The usertypically expects to receive the memory in the erased state (i.e., FFH).

The defective block numbers can be stored at the end of an error freeblock. One or more data bytes may be required to store the information,depending on the number of defective blocks.

In one embodiment, the error free block is block 0 of the memory array.In an alternate embodiment, block 0 may not be the error free block. Insuch an embodiment, the first block determined to be defect-free isused. In another embodiment, the defective locations may be stored atthe end of each block that contains at least one defective location. Inthis case, the stored defect indication might be the columns that aredefective or some other defect indication that can be read by a user.

If no defective memory cells were discovered 103, the memory is erased109. In this case, the memory locations all read FFH, or some othererased state, and the memory is ready for use.

One type of error in a flash memory device is that some cells cannot beprogrammed. They may be stuck in the erased state of FFH. With such adefect, the end user may not be able to tell that the block is bad sincethe FFH simply indicates that the block is erased. In this embodiment, apredetermined pattern (e.g., AAH) can be stored at some predefinedlocation in the block (e.g., the end of the block) after the memorydevice has been tested and it has been determined that the block can beprogrammed. The end user can then go to this defect indication locationand check for the predefined pattern. If the pattern is present, theuser knows that the block is good and can be programmed. If the patternis missing, the block is not programmable and is flagged as defective bythe memory controller.

Flash memory devices that incorporate the embodiments of the defectivememory block indication method of the present invention may bemanufactured in a NOR architecture, a NAND architecture, or some othertype of flash memory. In a NOR configuration, the cells are arranged ina matrix. The gates of each floating gate memory cell of the arraymatrix are connected by rows to wordlines and their drains are connectedto column bitlines. The source of each floating gate memory cell istypically connected to a common source line.

FIG. 2 illustrates a simplified diagram of a typical NAND flash memoryarray of the present invention. The memory array of FIG. 2, for purposesof clarity, does not show all of the elements typically required in amemory array. For example, only two bitlines are shown (BL1 and BL2)when the number of bitlines required actually depends upon the memorydensity. The bitlines are subsequently referred to as (BL1-BLN).

The array is comprised of an array of floating gate cells 201 arrangedin series strings 204, 205. Each of the floating gate cells 201 arecoupled drain to source in each series chain 204, 205. A word line(WL0-WL31) that spans across multiple series strings 204, 205 is coupledto the control gates of every floating gate cell in a row in order tocontrol their operation. The bitlines (BL1-BLN) are eventually coupledto sense amplifiers (not shown) that detect the state of each cell.

In operation, the wordlines (WL0-WL31) select the individual floatinggate memory cells in the series chain 204, 205 to be written to or readfrom and operate the remaining floating gate memory cells in each seriesstring 204, 205 in a pass through mode. Each series string 204, 205 offloating gate memory cells is coupled to a source line 206 by a sourceselect gate 216, 217 and to an individual bitline (BL1-BLN) by a drainselect gate 212, 213. The source select gates 216, 217 are controlled bya source select gate control line SG(S) 218 coupled to their controlgates. The drain select gates 212, 213 are controlled by a drain selectgate control line SG(D) 214.

Each cell can be programmed as a single bit per cell (SBC) or multiplebits per cell (i.e., multilevel cell—MLC). Each cell's threshold voltage(V_(t)) determines the data that is stored in the cell. For example, ina single bit per cell, a V_(t) of 0.5V might indicate a programmed cellwhile a V_(t) of −0.5V might indicate an erased cell. The multilevelcell may have multiple V_(t) windows that each indicate a differentstate. Multilevel cells take advantage of the analog nature of atraditional flash cell by assigning a bit pattern to a specific voltagerange stored on the cell. This technology permits the storage of two ormore bits per cell, depending on the quantity of voltage ranges assignedto the cell.

During a typical prior art programming operation, the selected wordlinefor the flash memory cell to be programmed is biased with a programmingpulse at a voltage that is greater than 16V. A verification operationwith a wordline voltage of 0V is then performed to determine if thefloating gate is at the proper voltage (e.g., 0.5V). The unselectedwordlines for the remaining cells are typically biased at approximately10V during the program operation. Each of the memory cells is programmedin a substantially similar fashion.

FIG. 3 illustrates a functional block diagram of a memory device 300that is coupled to a processor 310. The processor 310 may be amicroprocessor or some other type of controlling circuitry. The memorydevice 300 and the processor 310 form part of an electronic system 320.The processor 310 is capable of generating memory commands to the memorydevice 300. The memory device 300 has been simplified to focus onfeatures of the memory that are helpful in understanding the presentinvention.

The array of flash memory cells 330 may be comprised of the flash memorycells as described previously with reference to FIG. 2. In an alternateembodiment, the memory array 330 is a NOR memory array.

The memory array 330 is arranged in banks of rows and columns. Thecontrol gates of each row of memory cells is coupled with a wordlinewhile the drain and source connections of the memory cells are coupledto bitlines. As is well known in the art, the connections of the cellsto the bitlines determines whether the array is a NAND architecture or aNOR architecture.

An address buffer circuit 340 is provided to latch address signalsprovided on address input connections A0-Ax 342. Address signals arereceived and decoded by a row decoder 344 and a column decoder 346 toaccess the memory array 330. It will be appreciated by those skilled inthe art, with the benefit of the present description, that the number ofaddress input connections depends on the density and architecture of thememory array 330. That is, the number of addresses increases with bothincreased memory cell counts and increased bank and block counts.

The memory device 300 reads data in the memory array 330 by sensingvoltage or current changes in the memory array columns usingsense/buffer circuitry 350. The sense/buffer circuitry, in oneembodiment, is coupled to read and latch a row of data from the memoryarray 330. Data input and output buffer circuitry 360 is included forbi-directional data communication over a plurality of data connections362 with the controller 310. Write circuitry 355 is provided to writedata to the memory array.

Control circuitry 370 decodes signals provided on control connections372 from the processor 310. These signals are used to control theoperations on the memory array 330, including data read, data write(program), and erase operations. The control circuitry 370 may be astate machine, a sequencer, or some other type of controller that canexecute the embodiments of the defective memory indication method of thepresent invention.

The control circuitry 370 knows which memory address in one or morememory blocks, depending on the embodiment, is the defect indicationlocation. The control circuitry 370 can then read this location whenpowered-up by the user to determine which blocks are not usable.

The flash memory device illustrated in FIG. 3 has been simplified tofacilitate a basic understanding of the features of the memory. A moredetailed understanding of internal circuitry and functions of flashmemories are known to those skilled in the art.

CONCLUSION

In summary, the embodiments of the memory block defect identificationmethod of the present invention provide a flash memory device with anon-volatile indication of bad memory blocks. The memory defectindication is generated by the manufacturer during the initial testingprocess, thus relieving the controller from having to regenerate thedefective memory block map when the memory powered up at a later date bythe memory user.

In another embodiment, by writing a predetermined pattern in apredefined location in each block, the end user can check this locationto determine if the block has been checked for errors. The patternindicates the result of the error check while also indicating that theblock is writable.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.Accordingly, this application is intended to cover any adaptations orvariations of the invention. It is manifestly intended that thisinvention be limited only by the following claims and equivalentsthereof.

1. A memory device, configured to store in the memory device anindication of a location of a block of memory cells of the device thathas been determined to be defective.
 2. The memory device of claim 1,wherein the indication is stored in another block of the memory cells ofthe device that is different than the defective block.
 3. The memorydevice of claim 2, wherein the other block comprises a block of memorycells that has been determined to be free of defects.
 4. The memorydevice of claim 1, wherein the indication comprises a block number. 5.The memory device of claim 2, wherein the indication is stored at an endof the other block.
 6. The memory device of claim 2, wherein the otherblock comprises a first block of memory cells of the memory devicedetermined to be defect free.
 7. The memory device of claim 1, whereinthe indication of the location comprises indications of locations of aplurality of blocks of memory cells of the device determined to bedefective.
 8. The memory device of claim 1, wherein the indication isstored at the end of the block of memory cells.
 9. The memory device ofclaim 8, wherein the indication comprises a column of the block ofmemory cells that contains a defective location.
 10. A memory devicecomprising a block of memory cells, wherein a programmed pattern of datais stored in a block of memory cells that indicates that the block ofmemory cells is programmable.
 11. The memory device of claim 10, whereinthe programmed pattern is stored in the block after the memory devicehas been tested and it has been determined that the block can beprogrammed.
 12. The memory device of claim 10, wherein the programmedpattern is stored at a defect indication location in the block.
 13. Thememory device of claim 12, wherein the defect indication location is atthe end of the block.
 14. The memory device of claim 12, furthercomprising control circuitry configured to read the defect indicationlocation of the block to determine whether the block is usable.
 15. Thememory device of claim 12, further comprising control circuitryconfigured to read the defect indication location of the block todetermine whether the block is programmable.
 16. The memory device ofclaim 1, further comprising control circuitry configured to read theindication to determine whether the block is usable.
 17. The memorydevice of claim 1, further comprising control circuitry configured toread the indication to determine whether the block is programmable
 18. Asystem, comprising: a processor; and a memory device coupled to theprocessor, wherein an indication of a location of a block of memorycells of the device that has been determined to be defective is storedin the memory device.
 19. A system, comprising: a processor; and amemory device coupled to the processor and comprising a block of memorycells, wherein a programmed pattern of data is stored in a block ofmemory cells that indicates that the block of memory cells isprogrammable.
 20. The system of claim 19, wherein the block is notprogrammable if the pattern is missing.